Optimization of Rns Fir Filters for 6-inputs Lut Based Fpgas

In this paper optimized Residue Number System (RNS) arithmetic blocks to better exploit some of the architectural characteristics of the last generation FPGAs are presented. The implementation of modulo m adders, constant and general multipliers, input and output converters is presented. These architectures are based on moduli sets chosen in order to optimally use the six inputs Look-Up Tables (LUTs) available in the Complex Logic Blocks (CLBs) of the new generation FPGAs. Experiments based on the implementation of Finite Impulse Response (FIR) filters characterized by different number of taps and wordlengths shows that the use the RNS together with suitable moduli sets optimally fits the six inputs LUTs of the last generation FPGAs architectures.